DK-DEV-5SGXEA7N【PDF 32/527 页】KIT DEV STRATIX V FPGA 5SGXEA7

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2-10

Embedded Memory Modes

SV51003

2013.05.06

Port A

1K x 16

1K x 20

16K x 1

Yes

—

8K x 2

Yes

—

4K x 4

Yes

—

4K x 5

—

Yes

Port B

2K x 8

Yes

—

2K x 10

—

Yes

1K x 16

Yes

—

1K x 20

—

Yes

Embedded Memory Modes

Caution: To avoid corrupting the memory contents, do not violate the setup or hold time on any of the

memory block input registers during read or write operations. This is applicable if you use the

memory blocks in single-port RAM, simple dual-port RAM, true dual-port RAM, or ROM mode.

Table 2-9: Memory Modes Supported in the Embedded Memory Blocks

This table lists and describes the memory modes that are supported in the Stratix V embedded memory blocks.

M20K

MLAB

Memory Mode

Single-port RAM

Support

Yes

Support

Yes

Description

You can perform only one read or one write operation at a time.

Use the read enable port to control the RAM output ports

behavior during a write operation:

? To retain the previous values that are held during the most

recent active read enable — create a read-enable port and

perform the write operation with the read enable port

deasserted.

? To show the new data being written, the old data at that

address, or a "Don't Care" value when read-during-write occurs

at the same address location — do not create a read-enable

signal, or activate the read enable during a write operation.

Simple dual-port

RAM

Yes

Yes

You can simultaneously perform one read and one write

operations to different locations where the write operation

happens on port A and the read operation happens on port B.

True dual-port

RAM

Yes

—

You can perform any combination of two port operations: two

reads, two writes, or one read and one write at two different clock

frequencies.

Altera Corporation

Embedded Memory Blocks in Stratix V Devices

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